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Presentation of an Efficient Design Methodology to develop IP-Core Functions for Control Systems: Application to the Design of an Antiwindup PID Controller
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| Author(s) |
E. Monmasson; L. Charaabi; I. Slama-Belkhodja |
| Abstract |
This paper presents an efficient design methodology to develop IP-Core functions in VHDL for
control systems. This methodology is able to cope with different optimization constraints such as the
reduction of both the development time and the execution time and the minimization of the consumed
resources of the chip. Our approach uses the AAA methodology (Algorithm Architecture Adequation),
which allows to rapidly develop and optimize the implantation of the DFG (Data Flow Graph) of an
algorithm. In order to illustrate the efficiency of this methodology, the authors present the implantation
of an antiwindup PID controller on a single Field Programmable Gate Array (FPGA) applied to the
control of a DC/DC converter. |
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| Filename: | EPE-PEMC2002 - T11-012 - Monmasson.pdf |
| Filesize: | 143.2 KB |
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| Type |
Members Only |
| Date |
Last modified 2004-05-13 by System |
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