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A Novel Voltage Clamped Snubber Circuit Topology Applied for Multilevel Inverter and Its Low Power Loss Operations
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| Author(s) |
M. Yamamoto; S. Sato; M. Nakaoka |
| Abstract |
This paper presents a novel prototype of lowered loss snubber circuit topology suitable for multilevel
voltage source type inverter and rectifier for high power applications. The reduced power loss characteristics
and voltage capability performances of the proposed voltage clamped snubber circuit are evaluated
in comparison with conventional RCD-snubber circuit designed for 4-Level voltage-fed inverter using
IGBTs on the basis of exprimental results. |
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| Filename: | EPE-PEMC2002 - T1-047 - Yamamoto.pdf |
| Filesize: | 575.7 KB |
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| Type |
Members Only |
| Date |
Last modified 2004-05-12 by System |
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