A Single Critical Mask Process for Manufacturing Very Large Area MOS-Controlled Power Transistors | ||||||
Author(s) | D. W. Tsang | |||||
Abstract | The ability to remove heat from a device constitutes the most fundamental limitation to the performance of a high power device. Other figures of merit such as response time and ease of control further differentiate one device type from another. In the past, solutions for higher power for MOS devices have meant fine linewidth where incremental packing density improvement chisels away at forward drop. More recently, newer device configurations (IGBTs and MCTs) employing conductivity modulation, higher mobility semiconductors (SiC, III-V compounds, Diamond) are better thermal property packaging materials combine to promise faster and higher power devices in the future. In this paper, the concept of effectively linking processing procedure with device design to permit manufacturing of very large area devices is presented. Large device area is central to high power appliactions. |
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Type | Members Only | |||||
Date | Last modified 2006-04-19 by System | |||||
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