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A high voltage, high current transmission-line-pulse testbench for the reliability investigation of deep depletion, metal-insulator-semiconductor trench capacitors
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| Author(s) |
Camille GILLOT, René ESCOFFIER, Bruno ALLARD, Larry BUFFLE, Frédéric VOIRON |
| Abstract |
This paper presents a work-in-progress design of a transmission-line-pulse testbench (TLPTB) for the investigation of the reliability of deep depletion, on-metal insulator semiconductor (MIS) capacitor at wafer level scale.Firstly, we describe the capacitor (DUT) and the targeted application requiring the investigation of reliability: a snubber for wide-band gap (WBG) transistor. Then we explain the capacitor ageing mechanism induced specifically in the snubber application. We need to stress the capacitor repeatedly under high voltage (1000 V) and high current (100 A). The TLPTB is suitable for such stress pattern. The design is based on SPICE simulation prior to a board layout design. The theoretical subsection describes the expected stress sequence. The physical implementation is discussed along with a measurement setup. |
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| Filename: | 0333-epe2025-full-15310318.pdf |
| Filesize: | 1.232 MB |
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| Type |
Members Only |
| Date |
Last modified 2025-08-31 by System |
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