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Minimization of parasitic capacitance for proper function of 3 level ANPC with GaN switches
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| Author(s) |
Qian LI, Guenter SCHROEDER |
| Abstract |
With GaN semiconductors the slew rate of the voltage dv/dt is a problem which can cause electromagnetic interference (EMI) and undesirable turning on of semiconductors. In this paper different design examples for the PCB (printed circuit board) for the switches and their drivers are introduced. An optimized design is proposed. |
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| Filename: | 0108-epe2023-full-12222343.pdf |
| Filesize: | 2.626 MB |
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| Type |
Members Only |
| Date |
Last modified 2023-09-24 by System |
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