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   Non-parasitic induced transient overvoltage in ANPC topology due to critical switching sequences   [View] 
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 Author(s)   Michael GEISS 
 Abstract   This paper describes a semiconductor overvoltage in an Active-Neutral-Point-Clamped Converter(ANPC). This overvoltage occurs in case of inductive load when the output voltage of the ANPCchanges its polarity. In case of a grid inverter this occurs twice per grid period at the voltage zerocrossing. It can be observed in most of the ANPC-based power electronics with classical PWMpatterns and can reach the full DC-Link voltage. Although the ANPC is a well-known and widelyspread topology there has been no particular concern in literature about this effect yet. From our pointof view, the reason for this is a generous semiconductor dimensioning in terms of blocking voltageutilization and the limited energy due to the nature of the overvoltage. Nevertheless, this overvoltagecould become a problem in modern designs when SiC MOSFETs are used, and their Safe OperatingAreas (SOA) are pushed even further to the limits.The shown overvoltage is not a switching overshoot due to parasitic inductances and high switchingspeeds. It cannot be explained by 'hazardous' switching states either.In the following, the emergence is described in detail and a theoretical model is introduced andevaluated by simulations and measurements. Afterwards, methods to avoid the overvoltage are shownand a risk estimation is performed. 
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Filename:0364-epe2022-full-15560410.pdf
Filesize:656.7 KB
 Type   Members Only 
 Date   Last modified 2023-09-24 by System