| Abstract |
In multi-level inverters in particular, the switching blocking time (dead-time) can lead to undesired voltage errors, which have a significant influence on the current quality. When changing between levels, clamping must be applied to ensure the minimum switch-on and switch-off time of the power electronics. The trend towards higher switching frequencies and smaller grid filters increases the difficulty of feeding in a standard-compliant output current, especially in active neutral-point-clamped (ANPC) inverters. In this paper, the effects of clamping and a compensation method are simulated for ANPC inverters and verified on a 3-level grid forming demonstrator. |
