| Abstract |
In this paper two modified three-phase dv/dt filter networks are analysed. They're investigated in a fastswitching SiC-MOSFET inverter system with the primary purpose of reducing the steep voltage slopescaused by the wide bandgap semiconductor devices at the output of the inverter. This should preservethe insulation system of a connected electrical load machine from partial discharges and deterioration.The necessity of damping down the voltage slopes outside of the inverter can arise from the possibilityof lower switching losses and more favourable temperatures within the inverter. An additional filter ofcourse will cause power losses depending on it's parameters. Hence, the influence of the passive filterparameters on those losses are an integral part of the analysis. In addition to the slope-damping of theinverter output voltage, the two discussed filter topologies should also challenge the conducted EMI ofthe system. Therefore, both of the circuits use special modifications to reduce the interference levelsintroduced by the fast switching inverter. Furthermore, a diode clamping of the filter output voltage tothe DC-link potentials is implemented and it's impact on the dv/dt reduction, filter losses and EMI isdiscussed. Generally, a higher filter inductance, meaning a lower necessary capacitance, will reducethe extra filter losses at the expense of a higher filter volume as well as additional oscillations of theoutput voltage. The diode clamping leads to a significantly less overshoot and ringing of the resultingvoltages, but to an increase of the measured losses. Finally, examining the influences of the differentfilter topologies, their parameters and the diode clamping on the conducted EMC behaviour, it will beshown that both of the modified topologies have the ability to reduce EMI levels in certain areas. |
