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   MARGIN IN THE JUNCTION-TEMPERATURE-RISE OF SEMICONDUCTOR-VALVE-ASSEMBLIES CAUSED BY THE STANDARD LOAD-DUTIES FOR TEST FOR MOTOR-DRIVE-SYSTEMS   [View] 
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 Author(s)   Y. Ikeda; M. Ubukata; J. Itsumi 
 Abstract   During last ten years, two kinds of the current rating systems concerning the equivalent load cycles and / or the test-duties for the semiconductor-valve-assemblies applied to the DC motor-drive-systems have been proposed. One is going to be published as the new Standard of the International Electrotechnical Commission after a long discussion of about twenty years, and the other was published as the Standard of the Japanese Electrotechnical Committee with much reference to the old IEC document around ten years ago. The paper discusses systematically the level of the margin in the junction-temperature-rises of the valves used for the assemblies designed strictly under the two rating-systems for various kinds of load-cycles as well as for the various transient thermal impedances and for the various dissipation characteristics. lt has been found that the IEC method introduces more margin in the junction-temperature-rise, in other words, it does overestimation of the capacity of the assemlies, particularly in cases of high peak - to - r.m.s.-current-ratio, low r.m.s.- to average-current-ratio and also relatively short load-cycle-period. 
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Filename:Unnamed file
Filesize:3.198 MB
 Type   Members Only 
 Date   Last modified 2021-02-23 by System