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   VARIABLE TOPOLOGY: A NEW APPROACH IN C.A.D.   [View] 
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 Author(s)   F. Boulos; C. Glaize 
 Abstract   This paper deals with the use of variable topology simulation of static converters which ensures a significant reduction of the order of the system to be resolved as well as the computational time allowing its use on standard micro-computers. After the presentation of the modelization of the semi-conductors, we indicate the principle of such a method of simulation. In particular, we show the methods used to simplify the initial schema of the converter. The generation of equations is automatic. To illustrate our work, we present the results obtained by simulating a chopper. We emphasize the form of the minimal topology obtained at each change of configuration by indicating the numbering of the branches with their entry and exit nodes, as well as the values of the voltage across turned off semi-conductors or conducting semi-conductors which become turned off. 
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Filename:Unnamed file
Filesize:2.671 MB
 Type   Members Only 
 Date   Last modified 2021-02-08 by System