| Filename: | 0380-epe2020-full-13341917.pdf |
| Filesize: | 1.345 MB |
| Mitigating Drain Source Voltage Oscillation with Low Switching Losses for SiC Power MOSFETs Using FPGA-Controlled Active Gate Driver | ||||||
| Author(s) | Zheming LI | |||||
| Abstract | In order to improve the switching performance of SiC MOSFETs at turn-off, the drain-source voltageoscillation should be mitigated with low switching losses. To achieve this improvement, an approach,which uses an FPGA-controlled active gate driver with two level switchable gate resistances, isinvestigated and presented in this paper. To ensure the performance of this approach for varyingoperating points in a wide range, three methods are shown and compared to find the best solution. | |||||
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| Type | Members Only | |||||
| Date | Last modified 2021-01-18 by System | |||||
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