| Abstract |
This paper presents the adaptation of a 3D integration concept previously used with vertical devices to lateral GaN devices. This 3D integration allows to reduce loop inductance, to ensure moresymmetrical design with especially limited Common Mode emission, thanks to a low middle pointstray capacitance. This reduction has been achieved by both working on the power layout andincluding a specific shield between the devices and the heatsink. The performances of this 3D layouthave been verified in comparison with a more conventional 2D implementation, using bothsimulations and measurements. |
