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1Chip Process of LDMOS and BiCMOS used for Battery Charger IC
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| Author(s) |
C. K. Jeon; J. J. Kim; Y. S. Choi; M. H. Kim; S. L. Kim; H. S. Kang; C. S. Song |
| Abstract |
High Voltage LDMOS and control circuits have been integrated on the same chip which is a newly
proposed 1-chip process for smart power IC with no epi. layer. This paper describes a uniquely
designed layout and process architecture. When compared to 700V sustaining voltage and 0.55§Ùcm2
Ron,sp in conventional layout, the proposed LDMOS structure shows low specific on-resistance of
0.37§Ùcm2 and high breakdown voltage of 800V. And the method of effective ESD protection in
LDMOS with senseFET was proposed. |
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| Filename: | EPE2001 - PP00180 - Jeon.pdf |
| Filesize: | 1.271 MB |
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| Type |
Members Only |
| Date |
Last modified 2004-03-10 by System |
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