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OPTIMIZATION OF BV-Ron-Cgd OF POWER VDMOS TRANSISTORS
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| Author(s) |
M. Le Helley; J. P. Chante |
| Abstract |
The trade-off between the on-state resistance, the breakdown voltage and the gate-drain capacitance of power VDMOS transistors is studied by numerical methods. A new structure is proposed. A gain for the active area (27 %) and a decreasing of the gate-drain capacitance (x 0,2) without decreasing of the breakdown voltage are obtained. |
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| Filename: | Unnamed file |
| Filesize: | 1.798 MB |
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| Type |
Members Only |
| Date |
Last modified 2021-01-08 by System |
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