| Abstract |
In this paper, a universally applicable analytic benchmark is introduced to calculate optimal achievablehard switching losses. In a system, where the semiconductor has to meet given limitations like a maximum voltage slope, the benchmark calculates minimum reachable switching losses when the limits are completely exploited. In principle, two values, the maximum voltage slope du/dt and the commutation loop stray inductance Ls suffice to calculate an optimal hard switching waveform concerning switching losses. The benchmark is developed for high power applications, where the switching speed of the semiconductor is limited by the du/dt and the inductive switching overvoltage. The benchmark can be used for a fast evaluation of the effectiveness of certain optimization methods of the gate control or the effort of system parameter optimizations like reducing the stray inductance. In contrast to simulation tools it is independent of the MOSFET characteristic and gate driver, which allows an independent basic analysis. |
