| Abstract |
In this paper, a new optimal 3D Space Vector Modulation (SVM) for PUC5 converter is proposed. The algorithm add a common-mode voltage to the phase reference voltage that impose a trajectory for the voltage vector that lies over the external faces of the 3D Space Vector (SV) diagram. As a result, just three vectors are needed to synthesize the reference voltage. Compared to the classical 2D SV diagrams, the 3D SV diagram for PUC5, with the considered common-mode voltage, has not redundancies in phase coordinates, which requires a low computational effort for its implementation. In other hand, the vectors in phase coordinates, when described in switching states, can have up to four redundancies. This redundancies are used for minimizing a cost function composed by the ripple of the DC capacitor and the number of commutations of the semiconductor devices. In addition, the PUC5 topology presents some switches submitted to twice the blocking voltage of the others. To address this issue it is considered different weights in the cost function for these switches, which make it possible to reduce the overall commutation losses. The proposed modulation algorithm has been validated by extensive simulations. Furthermore, comparisons with other consolidated approaches in terms of Total Harmonic Distortion (THD), Weighted Total Harmonic Distortion (WTHD), capacitor voltage ripple and number of commutations demonstrate the good performance of the proposed SVM algorithm. |
