| Abstract |
This paper reports that the measurement of the thermal impedance of a power module via the Vce(T)-method is influenced by eddy currents in metal layers below the isolating ceramic. This influence is exemplified with measurements on a standard baseplate module. In these measurements, the apparent chip temperature evolution differs significantly if measured either at the auxiliary terminals or the main terminals. Experiments and simulations show good agreement and conclusively identify electromagnetic induction as origin of this difference. Finally, options to reduce the contribution of this effect to the measurement signal are discussed.This paper reports that the measurement of the thermal impedance of a power module via the Vce(T)-method is influenced by eddy currents in metal layers below the isolating ceramic. This influence is exemplified with measurements on a standard baseplate module. In these measurements, the apparent chip temperature evolution differs significantly if measured either at the auxiliary terminals or the main terminals. Experiments and simulations show good agreement and conclusively identify electromagnetic induction as origin of this difference. Finally, options to reduce the contribution of this effect to the measurement signal are discussed. |
