| Abstract |
This paper presents the design and evaluation of an architecture based on a compact bit-serial, floating-point device for Fast Fourier Transform (FFT) computation in digital signal applications implementable on 32 bit ISA or EISA buses of 386/486 PCs. It is made of two ASIC chips, the array processor, made with 160 bit-serial processing elements (PEs) and able to compute up to 80 butterfly parallel computations that was originally developed as portion of a massively parallel processor for FFT, and the interface section for buffering and control, containing three corner turning dynamic register banks. An assembly program for the device management on the PC is proposed. Performance evaluations are presented, with comparisons made on commercially available devices. |
