| Filename: | Unnamed file |
| Filesize: | 3.522 MB |
| DYNAMIC BEHAVIOUR OF DIGITAL PHASE-LOCKED LOOPS IN A COMMUNICATION SYSTEM FOR DRIVES | ||||||
| Author(s) | B. Gick | |||||
| Abstract | The clock recovery in the Serial Real Time Communication System for Drives (SERCOS interface) is investigated. In order to regenerate the receiver clock and the incoming stream of data, all digital phase-locked loops (ADPLLs) are used. The dynamic behaviour of a chain of ADPLLs is analysed, the theoretical considerations are verified by measurements at an experimental ring. As a result, the constraints for mixing different kinds of ADPLLs in a ring are shown. | |||||
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| Type | Members Only | |||||
| Date | Last modified 2019-08-07 by System | |||||
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