| Abstract |
In this paper, two macromodels of the power V.DMOS transistors, compatibles with the circuit simulator SPICE, are described. Well suited for switching characteristics simulation, these macromodels are established for low voltage as well as high voltage devices (50V - 1000V) with the available current handling capability 2A-50A. A library of the SPICE model for commercial products covering these ranges is available now. It was used as a data base to define relationships between the model parameters. As a result, an "unified" V.DMOS model is proposed, it requires for a given technology only two parameters : i) drainsource breakdown voltage, ii) silicon chip area. A model builder program linked with SPICE, gives an 'exact" model for characterized transistors as well as an 'unified' model for new or unknown devices. This modeling takes into account the crystal chip temperature and includes several validation tests such as switching circuits. |
