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DESIGN METHODOLOGY & MODELlNG OF LOW INDUCTANCE PLANAR BUS STRUCTURES
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| Author(s) |
G. L. Skibinski; D. M. Divan |
| Abstract |
The minimization of undesirable parasitic inductance becomes vitally important given the dual constraints of higher frequency and higher power levels of modern power converters. This paper investigates the impedance of conventional conductor bus configurations and outlines a planar bus approach that results in extremely low inductance over a wide range of operating frequencies. |
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| Filename: | Unnamed file |
| Filesize: | 5.697 MB |
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| Type |
Members Only |
| Date |
Last modified 2019-05-23 by System |
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