Please enter the words you want to search for:

[Return to folder listing]

   MEDIUM-VOLTAGE LATERAL NMOS POWER DEVICES IN STANDARD CMOS TECHNOLOGY   [View] 
 [Download] 
 Author(s)   F. H. Behrens; S. Finco; M. I. Castro Simas 
 Abstract   Medium-voltage lateral structures for power NMOS devices, suitable for integration with standard low-voltage CMOS control circuits in Power IC's, are presented. Two device types were fabricated on 2.0 and 1.5 microns, N-well, 2 metal layer, 10-mask CMOS standard technologies. Design rules and device mask geometry were adapted for enlarging the operating voltage range till 160 volts. The LDD-NMOS transistor is based on the lightly doped drain concept. The LDSD-NMOS transistor applies the same concept for both source and drain terminals. ON-resistance as low as 9 to 11 mOhm.cm² and breakdown voltages from 20 to 160 volts were experimentally obtained. Monolithic integration of multiple switches with low-voltage control is possible, since structures are electrically compatible. 
 Download 
Filename:Unnamed file
Filesize:2.939 MB
 Type   Members Only 
 Date   Last modified 2019-05-16 by System