| Abstract |
This paper presents a driver topology intended for WBG devices with the goal of improving the switchingperformance. In particular, the initial delay time of the switching transient was targeted. In high powerand high frequency bridge converters, the dead time causes output voltage waveform distortion and increases losses. Shorter delay time leads to shorter dead time requirement. Simulations show that the delay time can be minimised by correctly implementing the suggested driver stage. For the experimental validation, an improvement of 6-8 ns was demonstrated while keeping the same di/dt and dv/dt as a conventional gate driver. The improvement increases with increasing gate resistance. |
