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Resolver-to-Digital Converter with Synchronous Demodulation for FPGA based Low-Latency Control Loops
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| Author(s) |
Alessandro LIDOZZI |
| Abstract |
This paper deals with a synchronous demodulation scheme to be used to obtain the speed and position from resolver position sensor. Proposed algorithm is intended to be implemented on a FPGA to provide the elaborated information for very low latency control loops. Moreover, resolver excitation circuit has been simplified working directly with a square wave signal. Resolver frequency behavior has been also taken into account due to the non-sinusoidal excitation. |
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| Filename: | 0399-epe2017-full-17084398.pdf |
| Filesize: | 798.5 KB |
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| Type |
Members Only |
| Date |
Last modified 2018-04-17 by System |
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