| Abstract |
This paper deals with the reductionof the switching energy losses of a SiC transistor by boosting its gate current. Notoriously, wide band-gap semiconductor transistors exhibit very fast switching performances, which provoke undesirables oscillations at high frequencies. An auxiliary circuit, located at the semiconductor device terminals, is developedto limit the electrical stresses, deleterious for the transistor integrity, and to reduce the EMC conducted interferenceswithout modifying the current and voltage slopes during the switching transition. Firstly, the SiC MosFET is characterized on SABER environment from MosFET template available on the library. The behavior of the obtained model is compared with Model Architect tool, available in the same environment. Experimental tests are carried out and confirm the behaviors predictedby simulation. The obtained results underlines the good accuracy and the merits of the simulation model developed in this work, despite the useof the power transistor in a complex configuration. |
