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IGBT Cell Optimization with Simulation and Comparison with Measurements
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| Author(s) |
H. Brunner; T. Laska; A. Porst |
| Abstract |
New simulation results are presented concerning the optimization of a planar. non-punchthrough IGBT. Lateral and vertical variations of a planar IGBT cell are carried out. A sufficiently large
powell spacing leads to a low drift resistance in the n layer . A decreasing of the powell deepness reduces the parasitic JFET effect. Cell optimization is done with a view to IGBT latch-up ruggedness. Our processed IGBT chip design is determined in accordance with the results of the numerical cell
optimization and shows the desired behavior. |
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| Filename: | Unnamed file |
| Filesize: | 319.3 KB |
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| Type |
Members Only |
| Date |
Last modified 2018-04-12 by System |
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