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Breakdown improvement and reliable driving of High-Voltage NMOS fabricated in fully implanted CMOS
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| Author(s) |
P. M. Santos; H. Quaresma; A. P. Silva; M. Lança |
| Abstract |
This paper discusses the viability of using last generation fully implanted digital CMOS technology to
develop a High-Voltage NMOS library for smart power integration. Devices are based in the classical
extended drain and in the fully CMOS compatible gate-shifting techniques to achieve experimental
breakdown voltages in the range of 22-30 V.
The trade-offs of using high overdrive voltages, above digital nominal supply, to reduce On-resistance
is also discussed. According to experiments on prototypes the gate oxide thickness is the most
important limitation to the maximum allowable gate voltage in order to achieve a long-term reliable
performance, especially in high-side symmetric transistors. Devices under excessive overdrive
voltages over long periods revealed threshold voltage and transconductance variations, due to gate
oxide degradation. |
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| Filename: | EPE2003-PP0575 - Santos |
| Filesize: | 906.9 KB |
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| Type |
Members Only |
| Date |
Last modified 2003-10-14 by Unknown |
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