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Low parasitic inductance multi-chip SiC devices packaging technology
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| Author(s) |
Bassem MOUAWAD |
| Abstract |
This paper presents a novel packaging structure which employs stacked substrate and flexible printed circuit board (PCB) to obtain very low parasitic inductance and hence feature high switching speed SiC power devices. A half-bridge module aimed at blocking voltage up to 2.5kV has been designed to accommodate 8 SiC JFETs and 4 SiC diodes. Electromagnetic simulation results reveal extremely low inductance values of the major loops. Then the prototyping of the designed package including the assembly process, all the electrical test to evaluate the electrical performance are presented. |
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| Filename: | 0469-epe2016-full-20424946.pdf |
| Filesize: | 1.057 MB |
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| Type |
Members Only |
| Date |
Last modified 2017-04-13 by System |
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