| Abstract |
This paper proposes a 'complementary inverter', which consists of p-channel and n-channel MOSFETsin a leg. This configuration can minimize dead time; therefore, harmonics generated by the dead timecan be eliminated, without any compensation controls. Possible leg configurations and appropriate gatedriver are discussed. Model for estimating dead time is shown and was confirmed by experiments witha half-bridge inverter. The minimum dead time of 130 ns was achieved in a fabricated prototype. Theadvantage of the minimum dead-time operation by the complementary topology was verified by applyingto a 400 W grid-tied inverter with 100 kHz switching frequency and a reduced impedance of the gridconnecting inductor to 1.5\% of the nominal, and 2.3\% current THD (total harmonic distortion) wasachieved. |
