| Abstract |
This paper investigates the physics of device failure during avalanche mode conduction for SiCMOSFETs. SiC devices have been shown to have superior electro-thermal ruggedness duringunclamped inductive switching (UIS) compared with similarly rated silicon IGBTs [1]. Failureduring UIS normally results from parasitic BJT latch-up which is exacerbated at higher temperatures[2, 3]. Measurements show that the total avalanche energy conducted by the device improves when theUIS occurs over longer avalanche duration with a smaller peak avalanche current as opposed to ahigher peak avalanche current over a shorter duration. This is due to the fact that cell-to-cell (or die-todie)variations in electrical parameters are more critical during peak avalanche current conduction.Power MOSFETs are comprised to numerous FET cells internally connected to common source, drainand gate terminals and the density of which is determined by the cell pitch and die area. These FETcells are normally assumed to be uniform in electro-thermal properties, however, there are variationsin parameters like thermal resistance, gate resistance, oxide thickness, body doping, etc. Finite elementmodels of 2 FET cells within a MOSFET show how variations in gate resistance and thermalresistance (initial junction temperature) degrade the devices reliability under UIS and that this is morecritical for higher avalanche currents. The finite element models are supported by experimentalmeasurements designed to emulate the effect of inter-cell variation. |
