| |
TRANSIENT BEHAVIOUR OF ISOLATION ARCHITECTURES IN SMART POWER INTEGRATED CIRCUITS
| [View]
[Download]
|
| Author(s) |
Evgueniy N. STEFANOV; Georges CHARITAT; Nicolas NOLHIER; Pierre ROSSEL |
| Abstract |
We report an electrical analysis of the transient interaction between High Voltage devices and Low Voltage
CMOS cell integrated on the same chip and separated by a mixed Dielectric/Junction, p-n juction and dielectric isolation architectures. The latchup dynamic of the CMOS commutation cell on transient high voltage biasing is studied and
compared for the mentioned isolation concepts. The transient analysis is made by the rigorous 2-D numerical modeling program S-PISCES. |
| Download |
| Filename: | Unnamed file |
| Filesize: | 651.9 KB |
|
| Type |
Members Only |
| Date |
Last modified 2016-04-07 by System |
| |
 |