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SIMULATION / OPTIMIZATION OF IC VDMOS LAYOUT-DEPENDENT ELECTROSTATICS
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| Author(s) |
R. Thoma; J. Victory; J. Buxo; T. Zirkle; I. Pages; P. Raguet |
| Abstract |
The SPICE-model published by Victory et al. was improved for circuit simulation and optimization of high performance large area vertical DMOS (VDMOS) devices. This model is based on an exact analytical approach derived from the underlying electrostatic principles. It can handle various types of new layouts in two metal layers and compares well with measurements and more detailed numerical simulations. The latter simulations were perforn1ed in a 3D Poisson Equation solver and included all the details of the 2D layout of both metal layers as well as parasitic effects due to the bond wires of the package. |
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| Filename: | Unnamed file |
| Filesize: | 633.5 KB |
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| Type |
Members Only |
| Date |
Last modified 2016-02-11 by System |
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