| Abstract |
While the semiconductor industry struggles with the inherent trade-offs of solid-state devices, serialization of power switches, like the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) or the Insulated Gate Bipolar Transistor (IGBT), has been proven to be an advantageous alternative to acquire a high-efficient, high-voltage, fast-switching device. More than twenty years of research, on the serialization of solid-state devices, have resulted into several different stacking concepts. Among the prevailing ones, the gate balancing core technique, which has demonstrated very good performance in strings of high-power IGBT modules. In this paper, the limitations of the gate balancing core technique, when employed to serialize low or medium power off-the-shelf switches, are identified via experimental results. A new design specification for the interwinding capacitance of the employed transformer is derived to address those limitations, leading to a revised version of the technique. The effectiveness and the applicability of the revisited gate balancing core technique are verified, via experiments conducted on a string of two off-the-self, non-matched MOSFETs, installed in an inductively loaded step-down converter. |
