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FPGA-based Switched Reluctance Motor Drive and DC-DC Converter Models for High-Bandwidth HIL Real-Time Simulator
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| Author(s) |
Christian DUFOUR, Sebastien CENSE, Jean BELANGER |
| Abstract |
In this paper, we describe an FPGA implementation of a Switched Reluctance Motor Drive (SRM) and an H-bridge Buck-Boost converter targeted for Hardware-In-the Loop (HIL) testing of modern SRM controllers. With sample times near 100 nanoseconds, these FPGA models allow the HIL simulation of SRM drive and boost converter with switching frequencies in the 50-100 kHz range because of the very high sampling rate of the FPGA. The models are also integrated into the RT-LAB real-time environment and directly linked with the simulator I/Os, providing ultra-low HIL gate-in-to-current-out latency, suitable for testing modern motor controllers. |
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| Filename: | 0412-epe2013-full-21352176.pdf |
| Filesize: | 579.3 KB |
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| Type |
Members Only |
| Date |
Last modified 2014-02-09 by System |
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