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Space Vector Modulation Scheme to Minimize Common-Mode Voltage generated by a Three-Phase Hybrid Multilevel Inverter
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| Author(s) |
Tiago Kommers JAPPE, Samir Ahmad MUSSA, Marcelo Lobo HELDWEIN, Domingo Ruiz CABALLERO, Antonio CASTILLO |
| Abstract |
This paper proposes the implementation of a space vector modulation (SVM) scheme to reduce thecommon-mode voltage of a symmetrical hybrid five-level inverter operating at high modulation index.The proposed modulation is implemented in a DSC–Digital Signal Controller. It employs vectors thatprevent voltage vectors that impose high common-mode voltages at the converter load. Experimentalresults are presented in order to validate the proposed modulation scheme. |
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| Filename: | 0734-epe2011-full-23202529.pdf |
| Filesize: | 272.9 KB |
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| Type |
Members Only |
| Date |
Last modified 2012-01-26 by System |
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