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FlePs: a power interface for Power Hardware In the Loop
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| Author(s) |
Andrea BENIGNI, Alexander HELMEDAG, Adil ABDALRAHMAN, Grzegorz PILATOWICZ, Antonello MONTI |
| Abstract |
Power Hardware In the Loop (PHIL) is a recognized technique to extend Hardware In the Loop tests to power level by enforcing conservation of energy at the connection between real and virtual portions of the system under test. In this paper we present the design of a flexible hardware interface to perform PHIL testing: some experimental results are also presented |
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| Filename: | 0825-epe2011-full-19230945.pdf |
| Filesize: | 573.9 KB |
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| Type |
Members Only |
| Date |
Last modified 2012-01-26 by System |
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