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Circuit for reducing devices voltage stress due to DC-link capacitor voltage ripple in a Neutral-Point-Clamped inverter
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| Author(s) |
Georgios ORFANOUDAKIS, Suleiman SHARKH, Michael YURATICH |
| Abstract |
The paper presents a circuit that reduces the voltage stress caused by DC-link capacitor voltage ripple on the switching devices of a three-level Neutral-Point-Clamped (NPC) inverter. The circuit is capable of halving the amplitude of the voltage ripple seen by the inverter devices. It is proposed as an alternative to over-sizing the inverter’s DC-link capacitors, or using capacitor-balancing PWM strategies that increase the switching frequency and associated losses. The structure and operation of the circuit are described and the ratings of its components are determined. The benefit it offers is compared to that of existing solutions, based on an example NPC inverter design. The results, verified using MATLAB-Simulink, indicate that the circuit can outperform other proposed balancing circuits, halve the DC-link capacitance and cover cases where the switching frequency cannot be increased. |
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| Filename: | 0530-epe2011-full-14555303.pdf |
| Filesize: | 250.8 KB |
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| Type |
Members Only |
| Date |
Last modified 2012-01-26 by System |
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