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A Method of Voltage Limiting and Distortion Avoidance for Islanded Inverter-Fed Networks under Fault
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| Author(s) |
Cornelis PLET, Tim GREEN |
| Abstract |
Inverter current limiting in islanded networks during unbalanced faults can cause voltage distortion. By using the control system to emulate a parallel impedance, this distortion can be avoided whilst current control is maintained and fault current is delivered to the fault. Experimental results from a 10 kVA inverter system are provided to verify the theoretical analysis that has been developed. |
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| Filename: | 0343-epe2011-full-12511452.pdf |
| Filesize: | 374.4 KB |
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| Type |
Members Only |
| Date |
Last modified 2012-01-26 by System |
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