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A Dual High-Speed PMSM Motor Drive Emulator with Finite Element Analysis on FPGA chip with Full Fault Testing Capability
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| Author(s) |
Yasuhiro INABA, Sébastien CENSE, Tarek OULD BACHIR, Hirofumi YAMASHITA, Christian DUFOUR |
| Abstract |
This paper presents a FPGA-based virtual motor drive system featuring two Permanent Magnet Synchronous Machine (PMSM) drives made with two-level IGBT/GTO inverters model with full fault capability. The inverters are implemented on the FPGA with a nodal solver, using floating point arithmetic, and support individual component faults, like a single IGBT open fault, as well as other non-standard modes, like cases with no IGBT gate signals and natural rectification. The motor model can be either linear d-q models or Finite Element Analysis models from JMAG-RT. The virtual motor drives are implemented on a Virtex-6 FPGA card and have a total latency near 1µs from the IGBT gate signal capture at Digital Inputs to motor currents at Analog Outputs and are therefore well adapted for HIL tests with high-speed machine with either PWM (up to 100 kHz) or hysteretic current control. Finally, the paper presents experimental accuracy validation made by a TIER-1 supplier for hybrid electric vehicle in Japan. |
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| Filename: | 0730-epe2011-full-18201218.pdf |
| Filesize: | 1.119 MB |
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| Type |
Members Only |
| Date |
Last modified 2012-01-26 by System |
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