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High-Resolution Digital PWM Controller for High-Frequency Low-Power SMPS
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| Author(s) |
Shuibao GUO |
| Abstract |
This paper proposes a high-resolution Digital-PWM (DPWM) architecture for high-frequency low-power Switching Mode Power Supply (SMPS). The proposed DPWM takes advantage of Digital Clock Man- ager (DCM) phase-shift characteristics available in FPGA, and combines a counter-comparator with a Multi-stAge-noise-SHaping (MASH) Delta-Sigma (Δ-Σ) modulator. An 11-bit effective prototype DPWM along with a digital PID control algorithm are experimentally verified by using a Virtex-II FPGA on a discrete low-power buck converter. Experimental results with constant switching frequency up to 4MHz validate the functionality of the proposed DPWM. In addition, the digital controller is imple- mented in a 0.35 µm standard CMOS. |
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| Filename: | 0117-epe2009-full-15442053.pdf |
| Filesize: | 1.117 MB |
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| Type |
Members Only |
| Date |
Last modified 2010-01-27 by System |
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