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FPGA design of a Robust Phase Locked Loop Algorithm for a Three Phase PWM Grid Connected Converter
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| Author(s) |
Mouna BEJAOUI, Ilhem SLAMA-BELKHODJA, Eric MONMASSON, Bogdan MARINESCU, Lotfi CHARAABI |
| Abstract |
The FPGA-design of a so-called rPLL for grid-connected renewable energy systems is developed. The design methodology leads to reduced consumed resources and time execution (1.14 µs with an XC3s400 FPGA device from Xilinx). Experimental results under healthy and faulty grid conditions illustrate the design effectiveness. |
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| Filename: | 0315-epe2009-full-17015107.pdf |
| Filesize: | 517 KB |
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| Type |
Members Only |
| Date |
Last modified 2010-01-27 by System |
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